1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device, and more particularly to a fabrication method of a semiconductor device containing p- and n-channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) which reduces the number of necessary photolithography process steps.
2. Description of the Prior Art
The complementary MOS (CMOS) structure is suitable for realizing denser integrated circuit devices (ICs) due to its minimized power consumption. For this reason, recently, almost all MOS ICs have had the CMOS structure.
An MOS IC having the CMOS structure, i.e., a CMOS IC, requires n-channel MOSFETs and p-channel MOSFETs provided on a silicon substrate.
Conventionally, CMOS ICs having the single well or tub structure have been fabricated. However, CMOS ICs having the twin well or tub structure have become popular because the twin tub structure enables optimization of the dopant concentration for both the n- and p-channel MOSFETs.
With the CMOS IC having the twin tub structure, (a) well formation, (b) threshold-voltage adjustment or channel doping, and (c) source/drain formation process step are required for each of the n- and p-channel MOSFETs, and each of the steps contains an impurity doping process. If each of the impurity doping process steps is done by lithography and subsequent ion-implantation techniques, each of the n- and p-channel MOSFETs needs two mask formation process steps. Therefore, the number of the necessary process steps for mask formation is six.
Also, to produce each of the n- and p-channel MOSFETs, (d) isolation oxide formation, (e) gate electrode formation, (f) contact hole formation, and (g) Aluminum (A1) interconnection film formation process steps are required, each of which needs a single photolithography process. Therefore, the total number of the necessary mask formation process steps is four for each of the n- and p-channel MOSFETs.
As a result, the total number of necessary mask formation process steps in CMOS IC fabrication is ten, which is specifically described below.
(1) P-well Formation Photolithography: A first photoresist film is formed and is patterned to selectively cover a PMOS active region where a p-channel MOSFET is formed. Then, a p-impurity is selectively ion-implanted into a semiconductor substrate to form a p-well region using the patterned first photoresist film as a mask.
(2) N-well Formation Photolithography: A second photoresist film is formed and is patterned to selectively cover an NMOS active region where an n-channel MOSFET is formed. Then, an n-impurity is selectively ion-implanted into the semiconductor substrate to form an n-well region using the patterned second photoresist film as a mask.
(3) Isolation Photolithography: After a silicon nitride film is formed on the entire substrate, a third photoresist film is formed on the silicon nitride film to be patterned so that it selectively covers the PMOS and NMOS active regions and exposes an isolation region. Then, the substrate is thermally and selectively oxidized using the patterned third photoresist film as a mask, resulting in an isolation oxide film on the isolation region.
(4) P-well Threshold Adjustment Photolithography: A fourth photoresist film is formed and is patterned to selectively cover the PMOS active region. Then, a p-impurity is selectively ion-implanted into the p-well region to adjust the threshold voltage of the n-channel MOSFET using the patterned fourth photoresist film as a mask.
(5) N-well Threshold Adjustment Photolithography: A fifth photoresist film is formed and is patterned to selectively cover the NMOS active region. Then, an n-impurity is selectively ion-implanted into the n-well region to adjust the threshold voltage of the p-channel MOSFET using the patterned fifth photoresist film as a mask.
(6) Gate Electrode Formation Photolithography: After a gate oxide film is selectively formed on the PMOS and NMOS active regions, a polysilicon film is deposited on the gate oxide film. A sixth photoresist film is formed on the polysilicon film to be patterned so that it selectively covers the channel regions of the n- and p-channel MOSFETs. Then, the polysilicon film is etched to form gate electrodes for the n- and p-channel MOSFETs using the patterned sixth photoresist film as a mask.
(7) N-Source/drain Region Formation Photolithography: A seventh photoresist film is formed to be patterned so that it selectively exposes the NMOS active region and a contact region for the n-well region. Then, an n-impurity is selectively ion-implanted into the substrate to form a pair of n-source/drain regions in the NMOS active region and an n.sup.+ -diffusion region in the PMOS region using the patterned seventh photoresist film as a mask.
(8) P-Source/drain Region Formation Photolithography: An eighth photoresist film is formed to be patterned so that it selectively exposes the PMOS active region and a contact region for the p-well region. Then, a p-impurity is selectively ion-implanted into the substrate to form a pair of p-source/drain regions in the PMOS active region and a p.sup.+ -diffusion region in the NMOS active region using the patterned eighth photoresist film as a mask.
(9) Contact Hole Formation Photolithography: After an interlayer insulator film is formed to cover the entire substrate, a ninth photoresist film is formed on the interlayer insulator film to be patterned so that it has contact holes that expose the n- and p-source/drain regions and the n.sup.+ - and p.sup.+ -diffusion regions.
(10) Interconnection Formation Photolithography: After an aluminum interconnection film is formed on the interlayer insulator film, a tenth photoresist film is formed on the interconnection film to be patterned so that it provides predetermined electrical interconnections. The patterned interconnection film is contacted with the n- and p-source/drain regions and the n.sup.+ - and p.sup.+ -diffusion regions, respectively.
As described above, the conventional standard fabrication method of the semiconductor device of the CMOS structure requires a lot of photoresist formation and patterning process steps, resulting in a complicated process sequence and necessary long development and fabrication periods, which leads to an increase in fabrication costs.
To solve the problems of the conventional standard fabrication method, various researches and proposals have been made to reduce the number of photoresist films.
A first conventional improved method was disclosed in the Japanese Non-Examined Patent Publication No. 4-343264 published in November 1992. In this method, a patterned photoresist film for n-well formation is used for a mask for a subsequent process of selective formation of a silicon dioxide (SiO.sub.2) film. The SiO.sub.2 film is obtained by the Liquid-Phase Epitaxy (LPE) technique. A p-well region is selectively formed in a semiconductor substrate using the selectively formed SiO.sub.2 film as a mask. This method results in the number of the patterned photoresist film formation steps being reduced by one.
A second conventional improved method was disclosed in the Japanese Non-Examined Patent Publication No. 3-171672 published in July 1991. In this method, a patterned photoresist film for n- or p-well formation is used for a mask for a subsequent process of threshold adjustment. An ion-implantation process for the well formation is performed at an acceleration energy that enables impurity ions to penetrate an isolation oxide film. The number of the patterned photoresist film formation steps can be reduced by two in this method.
A third conventional improved method was disclosed in the Japanese Non-Examined Patent Publication No. 62-149163 published in July 1987. In this method, a patterned photoresist film for n- or p-well formation is used for a mask for a subsequent process of source/drain formation. This method is specifically explained below referring to FIGS. 1A to 1E attached.
First, as shown in FIG. 1A, an isolation oxide film 22 is selectively formed on an n-silicon substrate 21 by the LOCal Oxidation of Silicon (LOCOS) technique, defining an NMOS active region for an n-channel MOSFET and a PMOS active region for a p-channel MOSFET. A gate oxide film 23 is formed on the NMOS and PMOS active regions. Gate electrodes 24a and 24b are formed on the gate oxide film 23 in the NMOS and PMOS active regions, respectively. To control an electric potential of a p-well region, i.e., a p-well potential, a patterned mask 24c is formed on the gate oxide film 23 in the NMOS active region. This mask 24c is made of the same material as that of the gate electrodes 24a and 24b and is formed during the same gate-formation process.
Next, as shown in FIG. 1B, a photoresist film 25a is formed over the substrate 21 and is patterned to selectively expose the NMOS active region. Then, a p-impurity is selectively ion-implanted into the substrate 21 to form a p-well region 26 using the patterned photoresist film 25a as a mask.
Then, a p-impurity is selectively ion-implanted into the channel region to adjust the threshold voltage of the n-channel MOSFET, which is termed a channel doping process. An n-impurity is selectively ion-implanted into the substrate 21 to form a pair of n-source/drain regions 27 in the NMOS active region, i.e., the p-well region 26.
Next, as shown in FIG. 1C, a photoresist film 25b is formed over the substrate 21 and is patterned to selectively expose the PMOS active region. Then, an n-impurity is selectively ion-implanted into the substrate 21 to adjust the threshold voltage of the p-channel MOSFET. A p-impurity is selectively ion-implanted into the n-substrate 21 to form a pair of p-source/drain regions 29 in the PMOS active region.
As shown in FIG. 1D, a photoresist film 25c is formed over the substrate 21 and is patterned to selectively expose the mask 24c. Then, the mask 24c is etched away using the photoresist film 25c as a mask, and a p-impurity such as boron (B) is selectively ion-implanted into the p-well region 26 to form a p.sup.+ -diffusion region 29c. The region 29c is used for controlling or fixing the well potential of the p-well region 26.
As shown in FIG. 1E, an interlayer insulator film 30 is then deposited to cover the entire substrate 21 and is patterned to form penetrating contact holes 31a, 31b and 32. The contact holes 31a exposes the pair of n-source/drain regions 27 for the n-channel MOSFET. The contact holes 31b expose the pair of p-source/drain regions 29 for the p-channel MOSFET. The contact hole 32 exposes the p.sup.+ -diffusion region 29c.
Finally, an A1 film is deposited on the interlayer insulator film 30 to be patterned, resulting in an interconnection or wiring film 33. The film 33 is contacted with the pair of n-source/drain regions 27 through the contact holes 31a, with the pair of p-source/drain regions 29 through the contact holes 31b, and with the p.sup.+ -diffusion region 29c through the contact hole 32.
As described above, the third conventional improved method disclosed in the Japanese Non-Examined Patent Publication No. 62-149163 requires seven photoresist film formation process steps, i.e., (1) isolation, (2) gate electrode formation, (3) n-source/drain formation, (4) p-source/drain formation, (5) ion-implantation mask formation, (6) contact hole formation, and (7) interconnection formation.
Compared with the above conventional standard method, the first conventional improved method reduces the number of the necessary photoresist film formation process steps by only one, and the second conventional improved method reduces the number by only two.
Even with the third conventional improved method shown in FIGS. 1A to 1E, seven photoresist film formation process steps are necessary. Also, this method has a problem that no n.sup.+ -diffusion region for controlling or fixing the substrate potential can be formed at the top surface of the substrate 21 and that no n-well region is provided in the substrate 21, which means the single-well structure.
Therefore, in the third conventional improved method, the substrate potential needs to be fixed to a predetermined value at the bottom or back surface of the substrate 21. However, this causes the tendency for the substrate potential of the p-channel MOSFET to fluctuate due to noises or the like, resulting in unstable operation and/or latch-up of the n- and p-channel MOSFETs.
Further, to realize the double-well or twin-tub structure, an n-well region may be formed in the substrate 21 by using the same process as used for the p-well region 26. However, another problem is that the potential of the n-well region becomes more unstable occurs. To solve this problem, the n-well region is required to be produced by using the same process as used for forming the p.sup.+ -diffusion region 29c in the p-well region 26. This means that the number of the necessary photoresist film formation steps increases by one and consequently, the number becomes eight in total.